Title:
ループ型クロック調整回路および試験装置
Document Type and Number:
Japanese Patent JP5028524
Kind Code:
B2
Abstract:
A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter.
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Inventors:
Kazuhiro Fujita
Kazuhiro Yamamoto
Masakatsu Suda
Kazuhiro Yamamoto
Masakatsu Suda
Application Number:
JP2010507149A
Publication Date:
September 19, 2012
Filing Date:
April 07, 2009
Export Citation:
Assignee:
Advantest Corporation
International Classes:
H03L7/081; H03K5/135; H03K5/26; H03K23/66; H03L7/093
Domestic Patent References:
| JP2001118385A | 2001-04-27 | |||
| JP2003069425A | 2003-03-07 | |||
| JP2003046388A | 2003-02-14 | |||
| JPH10285038A | 1998-10-23 |
Foreign References:
| WO2007072731A1 | 2007-06-28 |
Attorney, Agent or Firm:
Sakaki Morishita
Yusuke Murata
Tomoyuki Miki
Masaki Taiki
Yusuke Murata
Tomoyuki Miki
Masaki Taiki