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Patent Searching and Data


Title:
LOW AMPLITUDE CLOCK INPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH03181219
Kind Code:
A
Abstract:

PURPOSE: To attain the working to the low amplitude clock of an optional DC level by connecting one of both inputs of a comparator to a DC constant voltage source and the other input to the same voltage source via a resistance, and applying a low amplitude clock signal to the latter input via a capacitor.

CONSTITUTION: The base potential of a transistor TR 5 forming a comparator is fixed at a constant voltage level VSH via a voltage source 7. The base of another TR 4 is connected to the source 7 via a resistance 8 and steadily kept at a DC voltage level VSH. If the low amplitude clock of an optional DC voltage level is inputted to a clock input terminal 10 under such a condition, the difference between the DC component of the input clock and the potential of the source 7 is supplied to both ends of a capacitor 9. Therefore, a signal containing the AC component of a clock signal input superposed on the voltage of the source 7 is supplied to the base of the TR 4.


Inventors:
MORITAKE KAZUYUKI
Application Number:
JP32000089A
Publication Date:
August 07, 1991
Filing Date:
December 08, 1989
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F1/04; H03K5/08; (IPC1-7): G06F1/04; H03K5/08
Attorney, Agent or Firm:
Shigetaka Awano (1 person outside)