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Title:
低電力のモジュラス分周器ステージ
Document Type and Number:
Japanese Patent JP4988840
Kind Code:
B2
Abstract:
A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also receives a feedback modulus control signal from another MDS. When in the divide-by-two mode, the MDS divides by two regardless of the feedback modulus control signal. To conserve power, the first stage is unpowered when the MDS stage operates in the divide-by-two mode. When in the divide-by-three mode, the MDS stage either divides by two or by three depending on the feedback modulus control signal. To further reduce power consumption, the first stage is unpowered when the MDS stage is in the divide-by-three mode but is nonetheless performing a divide-by-two operation. A power-down transistor holds the output of the first stage at the proper logic level when the first stage is unpowered.

More Like This:
WO/2001/093427DUAL-MODULUS DIVIDER
Inventors:
Nara Song, Chu Chang
Su, Wen Jun
Application Number:
JP2009518531A
Publication Date:
August 01, 2012
Filing Date:
June 27, 2007
Export Citation:
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Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K23/66; H03K23/00
Domestic Patent References:
JP2002509376A
JP7307664A
JP10276084A
JP2001119292A
JP63290408A
Attorney, Agent or Firm:
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Tetsuya Kazama
Katsumura Hiro
Shoji Kawai
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen