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Patent Searching and Data


Title:
MANUFACTURE OF BIPOLAR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH07321290
Kind Code:
A
Abstract:

PURPOSE: To improve the quality with a high yield by eliminating the etching residual of a dielectric film.

CONSTITUTION: After forming a first SiO2 film 5 as a protecting film on an Si substrate 1 which has ara N epitaxially grown layer 3, an N+ diffused layer 6 to be the bottom electrode of an MIS type capacity is formed on the Si substrate 1. After forming a second SiO2 film 7 as an insulating film on the Si substrate 1, an opening 7a is formed on the second SiO2 film 7. An Si3N4 film 8 to be the dielectric of the MIS type capacity is formed in an area that includes the opening 7a. After forming a poly-Si film pattern 13 on the Si3N4 film 8, wet etching is performed for the Si3N4 film 8 using the poly-Si film pattern 13 as a mask. After forming a contact hole 7b on the top side of the N+ diffused layer 6 of the second SiO2 film 7, the natural oxide film of the contact hole 7b is removed by wet etching. Metal wiring 12 to be the top electrode of the MIS capacity is formed on the Si substrate 1.


Inventors:
KAJIYAMA MASAOKI
Application Number:
JP11252594A
Publication Date:
December 08, 1995
Filing Date:
May 26, 1994
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/28; H01L21/318; H01L21/822; H01L21/8222; H01L27/04; H01L27/06; (IPC1-7): H01L27/04; H01L21/28; H01L21/318; H01L21/822; H01L21/8222; H01L27/06
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)