Title:
MANUFACTURE OF MOSFET
Document Type and Number:
Japanese Patent JP3394562
Kind Code:
B2
Abstract:
PURPOSE: To enable manufacture of an MOSFET of LDD structure by a simple process, wherein the threshold voltage and the junction capacitance can be reduced and the number of processes and masks are not increased by a method, wherein a thick oxide mask and a sidewall spacer are used as masks, and ions are implanted in the state of self-alignment.
CONSTITUTION: A gate oxide film 43 is formed on a first conductivity-type substrate 14. After impurities for adjusting a threshold voltage are ion-implanted, a gate 44 of polysilicon is formed. A sidewall spacer 45, composed of an insulating film is formed. By using the spacer as a mask, ions are implanted, and second conductivity-type source/drain regions 46a, 46b of high concentration are formed. A thick insulating film 47 and a gate gap insulating film 48 are formed. After the sidewall spacer 45 has been eliminated, second conductivity type source/drain regions 49a, 49b of low concentration are formed by using the gate and the thick insulating film 47 as masks. Further, first conductivity type impurity regions 50a, 50b of low concentration are formed, so as to cover the regions 49a, 49b.
Inventors:
Zon Suk Gu
Application Number:
JP16333193A
Publication Date:
April 07, 2003
Filing Date:
June 08, 1993
Export Citation:
Assignee:
Ergi Semicon Company Limited
International Classes:
H01L21/336; H01L29/10; H01L29/78; (IPC1-7): H01L21/336; H01L29/78
Domestic Patent References:
| JP4139834A | ||||
| JP60263468A | ||||
| JP59197161A | ||||
| JP5283688A |
Attorney, Agent or Firm:
Masaki Yamakawa
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