PURPOSE: To improve alignment accuracy by eliminating resist application irregularities on an alignment mark of a semiconductor substrate.

CONSTITUTION: After resist 12 is applied on a semiconductor substrate 13 with an alignment mark 11, a resist configuration control plate 17 with a symmetrical configuration is pressed on the alignment mark 11 and a process for forming a resist film on and near the alignment mark to a symmetrical configuration is provided. Thereby, resist application irregularity on an alignment mark caused by viscosity of resist can be eliminated and position information of an alignment mark can be accurately detected. Thereby, it is possible to improve alignment accuracy of a lower layer pattern and an upper layer pattern in pattern formation of a semiconductor integrated circuit and to improve characteristic and yield of a semiconductor integrated circuit.