MANUFACTURE OF SEMICONDUCTOR DEVICE, AND THE SEMICONDUCTOR DEVICE

Japanese Patent JP2000196071

A

To provide a manufacturing method of a semiconductor device, which can reduce the gate resistance, by widening the width of a conductive layer on a gate electrode, without elongating the gate length.

After formation of an extension 5 within the topside of a silicon substrate 1, a silicon oxide film 6 and a silicon nitride film (7) are stacked over the entire substrate. Next, the silicon nitride film (7) and the silicon oxide film (6) are etched anisotropically in this order. Next, a silicon oxide film (10) is stacked all over, and then the silicon oxide film (10) is etched anisotropically. Then with the gate electrode 4 and the sidewall 12 as masks, ion implantation is performed to form an impurity region 13. Next, a silicon growth layer (15) is formed by performing silicon growth under conditions such that it has selectivity with respect to the silicon oxide film. Next, cobalt silicides (18) and 19 are made by performing heat treatment after stacking cobalt (17) over the entire surface. After that, unreacted cobalt (17) is removed.

OISHI TOSHIYUKI
NISHIDA MASAO
SAYAMA HIROKAZU

JP36909198A

July 14, 2000

December 25, 1998

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MITSUBISHI ELECTRIC CORP

H01L21/822; H01L21/28; H01L21/336; H01L21/762; H01L21/8238; H01L21/8239; H01L21/8242; H01L27/04; H01L27/092; H01L27/10; H01L29/43; H01L29/78; H01L21/20; (IPC1-7): H01L29/78; H01L21/336; H01L27/04; H01L21/822; H01L21/8238; H01L27/092; H01L27/10; H01L29/43

JPH10229187A	1998-08-25
JPH05218077A	1993-08-27
JP2000156502A	2000-06-06
JPH09172173A	1997-06-30

Shigeaki Yoshida (2 outside)

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