Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH01110749
Kind Code:
A
Abstract:
PURPOSE:To reduce the defect of an interwiring short-circuit in a multilayer interconnection structure and to improve the yield of a semiconductor device by a method wherein, after an interlayer insulating film is formed on the surface including lower layer wirings, the surface of the protrusion of the lower layer wiring and the surfaces, which are exposed in pinholes generated in the interlayer insulating film, of the lower layer wirings are oxidized to be converted into insulator layers. CONSTITUTION:Lower layer wirings 3 are selectively provided on an insulating film (Si oxide film) 2 formed on a semiconductor(Si) substrate 1 having a semiconductor element region and after an interlayer insulating film (Si oxide film) 4 is formed on the surface including the wirings 3, an oxidation treatment is performed to oxidize the surface of a protrusion 5, which reaches the surface of the film 4, of the wiring 3 or the surfaces, which are exposed in pinholes 6 generated in the film 4, of the wirings 3. After that, an upper lower wiring (Al wiring) is provided on the film 4. For example, the surfaces, which are exposed due to the defect of the Si oxide film 4 and so on, of Al wirings 3a and 3b are converted into Al oxide layers 7 using a 10minutes' anodic treatment, wherein an ethylene glycol solution saturated with ammonium borate is used, at 50V, a 30minutes' steam heating treatment at 400-500 deg.C or so on as an oxidation treatment for Al.
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Inventors:
YORIKANE MASAHARU
Application Number:
JP26846987A
Publication Date:
April 27, 1989
Filing Date:
October 23, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/31; H01L21/768; H01L23/522; (IPC1-7): H01L21/90; H01L21/95
Attorney, Agent or Firm:
Uchihara Shin