PURPOSE: To prevent disconnection and shorting of a metallic wiring which is formed on a layer insulation film, by providing the layer insulation film with ion implantation to form a difference in the doping amount between a flat surface of the layer insulation and its inclined surface and next by utilizing an etching speed difference based on a concentration difference of the doping amount to flatten the surface by wet etching.

CONSTITUTION: A layer insulation film 4 is formed on a MOS transistor whose source and drain are formed on a silicon substrate 2 by impurity diffusion. Next the whole surface is provided with ion implantation of phosphorus. Thereupon, the concentration of phosphorus implantation is high at a flat part of the layer insulation film 4 and low at an inclined surface of its recessed part. In succession, when the layer insulation film 4 is etched with a solution of hydrofluoric acid, the flat part of highly concentrated phosphorus implantation is etched in a great degree and the inclined part is etched in a small degree, and hence the layer insulation film 4 remains in the form of side walls of a gate electrode 8 and a field oxidizing film 10, and so the surface becomes smooth in its recessed and projected degrees. Thereafter, a PSG film 12 with a prescribed concentration of phosphorus is formed on the remaining layer insulation film 4a by a CVD method. This layer insulation film, whose surface is relaxed in its unevenness and flattened, can be formed accordingly.