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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6464315
Kind Code:
A
Abstract:

PURPOSE: To suppress a short channel effect by covering a whole semiconductor substrate with a thin insulating film having small impurity diffusion, removing part of the thin film, forming a thin metal film which becomes an impurity diffusion source on the whole substrate, and thermally annealing it.

CONSTITUTION: A thermal oxide film 7 is formed on a whole substrate by oxidizing the substrate in an oxygen atmosphere. Then, an N-channel transistor region is covered with a resist, the oxide film of a P-channel transistor is removed, and the resist is then exfoliated. Thereafter, a thin metal boron film 8 is formed on the substrate, and annealed to form a P+ type layer. Subsequently, after the remaining film 8 is converted into a BSG, it is removed by etching. Then, after an SiO2 film 10 is deposited on the whole substrate, an aluminum film is deposited, and patterned to form wirings 11. That is, the N-channel transistor region is covered with the film 7, and the film 8 is diffused as an impurity diffusion source to form a very shallow P+ type junction. Accordingly, a decrease in a gate threshold value voltage is reduced, and a short channel effect is remarkably suppressed.


Inventors:
KINUGAWA MASAAKI
Application Number:
JP22141187A
Publication Date:
March 10, 1989
Filing Date:
September 04, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/033; H01L21/225; H01L21/336; H01L21/822; H01L21/8234; H01L21/8242; H01L27/04; H01L27/088; H01L27/10; H01L27/108; H01L29/78; (IPC1-7): H01L21/225; H01L27/04; H01L27/08; H01L27/10; H01L29/78
Domestic Patent References:
JPS6276559A1987-04-08
JPS522165A1977-01-08
JPS62266829A1987-11-19
JPS61156858A1986-07-16
JPS60138974A1985-07-23
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)