To enable obtaining an offset structure without much increasing the number of processes by forming source/drain regions, by doping a silicon thin film, reducing a conducting film in the direction between the source/drain regions, and forming a gate electrode.

Patterns 1002, 1003 of silicon thin films and a pattern 1004 in contact with the patterns 1002, 1003 are formed on an insulating substrate 1001. For covering all the patterns, a gate-insulating film 1005, a conducting film 1006, a silicon oxide film 1007 are formed sequentially. A resist pattern 1008 is formed on the oxide film 1007 by using an optical exposure technique, and the oxide film 1007 is selectively etched by using the resist pattern 1008 as a mask. After that, the resist pattern 1008 is removed. The conductive film 1006 is etched, and a gate electrode 1009 is formed. Impurity ions are implanted, and a source region 1010 and a drain region 1011 are formed in the self-aligning manner. The gate electrode 1009 is etched so as to become thin.