Title:
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004281901
Kind Code:
A
Abstract:
To provide a manufacturing method of a semiconductor device wherein its impurity regions have shallow pn-junctions (shallow junctions).
The manufacturing method of the semiconductor device includes a step for forming element isolation regions 12 in a semiconductor layer 10, a step for forming a mask layer in the region to form a gate electrode, a step for performing the ion-implanting of impurities by using the mask layer as a mask, a step for removing the mask layer therefrom, a step for forming an oxide layer 20 on the surface of the semiconductor layer 10, a step for removing the oxide layer 20 therefrom, and a step for forming a gate insulation layer and the gate electrode in the region to form the gate electrode.
Inventors:
SAZE HIROKI
WATANABE YUKIMUNE
WATANABE YUKIMUNE
Application Number:
JP2003073930A
Publication Date:
October 07, 2004
Filing Date:
March 18, 2003
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/265; H01L29/78; (IPC1-7): H01L29/78; H01L21/265
Attorney, Agent or Firm:
Inoue Ichi
Yukio Fuse
Mitsue Obuchi
Yukio Fuse
Mitsue Obuchi