PURPOSE: To prevent the occurrence of a nonlinear error and to measure an unknown time highly precisely by setting a fractional time to be longer than the period of a clock pulse by a fractional time setting circuit.

CONSTITUTION: When a clock pulse (a) and a Q output C from a first RS flip- flop(FF) 3 set by a start pulse (b) being synchronous with the clock pulse are inputted to an AND circuit 1, this circuit makes a counter 2 start counting of the clock pulse (a). When a stop pulse (d) is inputted to second RS.FF 4 a prescribed time later, a fraction pulse (e) is inputted to a fractional time measuring part 5 and a two-stage shift register 6 and measurement of a fractional time is started. Meanwhile, the two-stage shift register 6 delivers a signal (f) to the first and second RS.FF 3 and 4 to reset them when the clock pulse (a) is inputted twice to it after the input of the fraction pulse (e), and thereby the counter 2 and the measuring part 5 are made to stop measurement. Based on a count value of the counter 2 and the time measured by the measuring part 5, the time from the start pulse to the stop pulse is determined. In this case, the fractional time is set to be longer than the period of the clock pulse by the fractional time setting circuit 6.