Title:
MEMORY ACCESS CONTROL DEVICE, AND MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2016027472
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method using a memory chip without receiving the influence of connection failure between a logic chip and the memory chip.SOLUTION: A memory access control device includes: a bit position information storage part for storing bit position information indicating one or more bit positions in a predetermined length of bit string; a reading part that tries to read out, from a memory, a bit string with the larger number of bits than the number of bits in a range of a storage area designated by a logic address, in a predetermined length unit; and a bit string extraction part that extracts a bit at a bit position indicated in the bit position information stored in the bit position information storage part, from the bit string taken out from the memory through the trial of read-out performed by the reading part, in a predetermined length unit. Integrated circuits are classified into ones for high performance and ones for popular performance depending on a usable bandwidth (S3320).SELECTED DRAWING: Figure 33
Inventors:
MORIMOTO TAKASHI
HASHIMOTO TAKASHI
HASHIMOTO TAKASHI
Application Number:
JP2015146438A
Publication Date:
February 18, 2016
Filing Date:
July 24, 2015
Export Citation:
Assignee:
PANASONIC IP MAN CORP
International Classes:
G06F12/16; G01R31/26; G11C5/00; G11C29/00; H01L21/60; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2003309183A | 2003-10-31 | |||
| JPH1196081A | 1999-04-09 | |||
| JP2003309183A | 2003-10-31 | |||
| JPH1196081A | 1999-04-09 |
Foreign References:
| WO2010085647A2 | 2010-07-29 |
Attorney, Agent or Firm:
Patent business corporation Nakajima intellectual property integrated office