Title:
メモリセル装置及びその製造方法
Document Type and Number:
Japanese Patent JP4027041
Kind Code:
B2
Abstract:
Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of a respective one of the layers run parallel to one another. The metallic lines of mutually adjacent layers run transversely with respect to one another.
Inventors:
Bernd Goebel
Siegfried Schwarzul
Siegfried Schwarzul
Application Number:
JP2000607220A
Publication Date:
December 26, 2007
Filing Date:
March 01, 2000
Export Citation:
Assignee:
Infineon Technolgies SC300 GmbH & Co.KG
International Classes:
G11C11/14; H01L21/8246; G11C11/15; G11C11/16; H01L27/105; H01L27/22; H01L43/08; H01L49/02
Domestic Patent References:
| JP10190090A | ||||
| JP10004227A | ||||
| JP2000196030A | ||||
| JP2002526909A |
Foreign References:
| US3604109 | ||||
| US5902690 |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel