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Title:
MEMORY CELL
Document Type and Number:
Japanese Patent JPS6455856
Kind Code:
A
Abstract:

PURPOSE: To miniaturize a memory cell by not forming a capacitor electrode layer at least on a part of a rim section of a groove.

CONSTITUTION: After peeling a resist film, a capacitor oxide film 111 is formed in an element area including a groove 107 formed by thermal oxidation. A photoresist 115 should be made to remain on a predetermined part including the area on the groove 107 by patterning after sequentially stacking a polycrystal silicon and a photoresist over the entire surface including the groove 107. Then, a capacitor electrode 113 is formed by means of isotropic etching, using the photoresist 115 as a mask. At this point, the polycrystal silicon in the vicinity of the rim part 107a of the groove is also removed. According to the constitution, which implements a structure where neither capacitor oxide film 111 nor capacitor electrode 113 are formed on the rim part 107a of the groove, the gate electrode 117 can be formed close to the groove 107, whereby the miniaturization of the memory cell can be achieved.


Inventors:
HIGUCHI TAKAYOSHI
MAEDA SATORU
Application Number:
JP21146287A
Publication Date:
March 02, 1989
Filing Date:
August 27, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/04; H01L27/10
Domestic Patent References:
JPS60152056A1985-08-10
JP62190752B
Attorney, Agent or Firm:
Hideaki Togawa