PURPOSE: To perform the reading operations of many processors simultaneously and to increase a total processing speed by accepting a write request according to the selection of a memory controller, which has the right of selection, among multiple memory controllers and by selecting a readout request by each device individually.

CONSTITUTION: Write and read request signals 12 and 13 from processors are inputted to write and readout request temporary storage circuits 14 and 15 of common memory controllers 11 and 11' and a processor's number having top priority is outputted through an encoder 5. This coded selection signal 6 is outputted to the other memory controller through an interface and also inputted to a selector 7, which receives a coded selection signal 6' from the other control memory controller at its opposite-side input. When a signal 8 having the right of selection is turned on or when a signal 19 indicating that there is a write request is turned off, the signal 6 of the device is selected by the selector 7 and when the signal 8 is turned off and the signal 19 is turned on, the signal 6' of the other device is selected, thereby returning a selection signal 10 to each processor through a decoder 9.