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Title:
MEMORY PROTECTION SYSTEM BY PROCESSOR
Document Type and Number:
Japanese Patent JPS57195394
Kind Code:
A
Abstract:

PURPOSE: To realize the hierarchy structure of programs and the separation of memory access ranges, and to achieve careful memory protection, by giving different priority levels to the programs.

CONSTITUTION: Priority information 4 outputted from a memory key register 1 is compared by a comparator 10 with priority information 8 from a protect key register 7, and section information 5 is compared by a comparator 11 with section information 9. A discriminating circuit 14 for discriminating whether access is allowed or not receives a priority information compaison signal 12, a section information comparison signal 13, and access limit information 6, and outputs a discrimination signal 15. An access error reporting circuit 16, once receiving a memory access signal 17, sends an interruption request signal 18 to a processor when the discrimination signal 15 shows an access error, and a write request signal 19 to a memory is inhibited by an NAND circuit 24.


Inventors:
MIYANAGA KEIZOU
KATSUKAWA TAKASHI
Application Number:
JP7840681A
Publication Date:
December 01, 1982
Filing Date:
May 23, 1981
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F12/14; G06F21/12; G06F21/62; G11C29/00; (IPC1-7): G11C29/00
Domestic Patent References:
JPS55116155A1980-09-06
JPS5617452A1981-02-19
JPS5679348A1981-06-29



 
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