PURPOSE: To secure the reduction of the power supply load by giving the refresh starting signal to the plural units of the memory module of the dynamic memory type through the memory control circuit with every module and in a time-division time.
CONSTITUTION: Memory system 3 comprises memory control unit MCU4, plural units of memory module 5 and memory interface 6. In MCU4, RFS timer signal 77 is generated from RFS timer circuit 70, signal 77 is counted by RFS address counter 71, and the signal which selects plural units of medule 5 in a time-division way is transmitted to module 5 via RFS address 61. Request signals 78 and 79 given from CPU1 and input/output control channel CH2 plus signal 77 are put into priority control circuit 72. At circuit 72, one of signals 78 and 79 is selected to be controlled so that it may not be produced non-synchronously with RFS start signal 60. As a result, the power supply load is reduced, obtaining a high-speed memory system in which the memory request is not disturbed by RFS.
BANDOU TADAAKI
FUKUNAGA YASUSHI
| JPS5073537A | 1975-06-17 | |||
| JPS5294044A | 1977-08-08 | |||
| JPS5042754A | 1975-04-18 | |||
| JPS5065630A | 1975-06-03 | |||
| JPS5419619A | 1979-02-14 | |||
| JPS53116044A | 1978-10-11 |
Next Patent: INFORMATION WRITE/ERASION METHOD TO NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT