Title:
MEMORY SYSTEM FOR CALCULATION CIRCUIT HAVING PIPELINE AND METHOD FOR PROVIDING PIPELINE FUNCTION UNIT WITH DATA
Document Type and Number:
Japanese Patent JP3935871
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a memory system for a calculation circuit having a pipeline including at least one function unit and an address generator for generating a memory address.
SOLUTION: A coherent cache memory responds to the address generator and is subjected to address designation by a memory address. The cache memory can generate a cache memory output. A noncoherent directoryless associative memory responds to the address generator and can be subjected to address designation by a memory address. The associative memory receives input data from the cache memory. The associative memory can generate an associative memory output to be transmitted to a functional unit. A comparison circuit compares the associative memory output with the cache memory output and asserts a mismatching signal when the associative memory output is not equal to the cache memory output.
Inventors:
David Arnold Ruick
Application Number:
JP2003347879A
Publication Date:
June 27, 2007
Filing Date:
October 07, 2003
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F12/08; G06F9/38; G06F12/12; (IPC1-7): G06F12/08
Domestic Patent References:
| JP2002312237A | ||||
| JP2001043130A | ||||
| JP8069411A | ||||
| JP4236644A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno
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