To easily specify a defective memory and a defective bit and to reduce a test time.

The same data as data supplied for writing in random access memories 6, 15 at the time of writing are inputted to inequality detecting circuits 7, 16 as an expected value at the time of reading, and the data are compared with data read out from the random access memories 6, 15 at the time of reading. Holding circuits 8, 17 hold the output signals of the inequality detecting circuits 7, 16, output registers 9, 18 store the output signals of the holding circuits 8, 17. These inequality detecting circuits, holding circuits, and output registers are provided for each bit constituting bit width of a random access memory. Also, the output registers 9, 18 are constituted of flip-flop with scan, and flip-flop with scan constitutes scan path for the bit of random access memories 6, 15 having the same address constitution.