To perform a function test and repair analysis processing in parallel by reflecting repair analysis processing to the next test.

A tester 30 performs the prescribed test for a semiconductor device, the result is stored in fail memory repair counter boards 60-6F. Repair CPUs 50 to 5F read out test results directly from the fail memory repair counter boards 60-6F, perform repair analysis processing. When data no-GO indicating that relief is impossible or data GO indicating that relief is possible are detected, the CPUs transmit data to a tester processor 20 side through memories 41-44 and a work station 10 sharing these data. After that, processing for obtaining a relief solution is performed for data which can be relieved. A tester processor 20 omits a second test and repair analysis processing corresponding to it for a semiconductor device which cannot be relieved. The calculation processing of a relief solution by repair CPUs 50 to 5F and the second function test by the tester 30 are performed in parallel for a semiconductor device which is judged as relievable.