Title:
メモリ試験装置及びメモリ試験方法
Document Type and Number:
Japanese Patent JP4119789
Kind Code:
B2
Abstract:
A pattern generator (20) generates an address while producing a test pattern for an examined memory (10), after receiving a failure memory count completion signal. A multiplexer (4) selects an address from an address pointer (3) and the pattern generator while generating back pattern in pattern generator after the count of defective number of bits respectively, for output to a failed memory (5). An independent claim is also included for dynamic RAM test method.
More Like This:
| JPS58218667 | INSPECTING METHOD OF INTEGRATED CIRCUIT |
| JP2008145266 | DEVICE TESTER |
| JP3740368 | Evaluation device for cell resistance in magnetoresistive memory |
Inventors:
Tsutomu Akiyama
Ginger ki phase
Park Jinei
Ginger ki phase
Park Jinei
Application Number:
JP2003146319A
Publication Date:
July 16, 2008
Filing Date:
May 23, 2003
Export Citation:
Assignee:
Yokogawa Electric Corporation
International Classes:
G01R31/28; G01R31/3183; G11C29/00; G11C29/56; H01L21/66
Domestic Patent References:
| JP61071500A | ||||
| JP8147997A |
Attorney, Agent or Firm:
Naotaka Ide