Title:
METHOD FOR AUTOMATICALLY DESIGNING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3171431
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To design the layout of a semiconductor integrated circuit of a master slice type through the use of a computer.
SOLUTION: A realization formula describing a combination of elements on a substrate for realizing the value of elements on a circuit, for example 'A/(B+C)' is reversely Polish converted into 'ABC+/' and the device data A, B, and C are read sequentially. When an operator + is read, device data 43 and 42 of C and B are taken out of a memory using a stack and positive terminal data of C and negative terminal data of B are grouped and serially operated. The result is stored in the memory as device data 44 after operation (B+C). When an operator/is read, the device data 44 and device data 41 of A are taken out of the memory using a stack. Their positive terminal data and negative terminal data are grouped and operated in parallel. The result is stored in the memory as device data 45 after operation (A/(B+C)).
Inventors:
Akiko Kurama
Application Number:
JP23795396A
Publication Date:
May 28, 2001
Filing Date:
September 09, 1996
Export Citation:
Assignee:
Matsushita Electronics Industrial Co., Ltd.
International Classes:
H01L21/82; G06F17/50; H01L27/118; (IPC1-7): H01L27/118; G06F17/50; H01L21/82
Domestic Patent References:
| JP3108369A | ||||
| JP61202453A | ||||
| JP7249748A | ||||
| JP63275141A | ||||
| JP59201143A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)