Title:
METHOD AND CIRCUIT FOR CONTROL OF VOLTAGE REFLECTION ON TRANSMISSION LINE
Document Type and Number:
Japanese Patent JPH07226666
Kind Code:
A
Abstract:
PURPOSE: To apply a terminal circuit to all cases where reflection becomes a trouble by permitting a clamping circuit giving prescribed inclination resistance to completely remove all reflections on a transmission line at time twice as much as the delay time of the transmission line with clamping. CONSTITUTION: A terminal clamp 46 gives a voltage/current characteristic and is connected to the tester 52 terminal part C of the transmission line 42. The other end of the transmission line 42 is connected to the port A of a device (DUT) 50 during a test. Transmission line reflection between the DUT 50 and the tester 52 is completely removed by time twice as much as the delay time of the transmission line 42. The output edges of the DUT 50, which are separated by time exceeding two-fold delay time, do not interfere each other. In the case of the DUT 50 driving the input terminal of the tester 52 at the logical steps of 0V-Vcc , the clamping circuit 46 gives a prescribed load to a tester terminal 46 equal to the characteristic impedance Z0 of the transmission line 42 only to voltage lower than voltage exceeding Vcc or 0V. It means that all reflections are removed within two-fold delay time of the transmission line 42 and the load becomes infinite.
Inventors:
KENISU AARU UIRUSHIYAA
Application Number:
JP25462392A
Publication Date:
August 22, 1995
Filing Date:
September 24, 1992
Export Citation:
Assignee:
SCHLUMBERGER TECHNOLOGIES INC
International Classes:
G01R31/319; H03K5/08; H03K19/0175; G01R31/28; H04L25/02; (IPC1-7): H03K19/0175; G01R31/28
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)
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