Title:
METHOD FOR DESIGNING LAYOUT OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2001291775
Kind Code:
A
Abstract:
To provide a method for designing the layout of an integrated circuit capable of effectively reducing a power source noise, and reducing the increase of a semiconductor chip area.
A power source noise generated in a circuit block is calculated by referring to a load capacity connected to the output terminal of the circuit block and a rising and falling time, and outputted as power source noise information in a step S5. A by-pass capacity for setting a prescribed power source noise level or less is selected from a noise by-pass capacity table 13 by referring to the power source noise information and the noise by-pass capacity table 13 in a step S6.
Inventors:
WAKAGI KEISUKE
Application Number:
JP2000106088A
Publication Date:
October 19, 2001
Filing Date:
April 07, 2000
Export Citation:
Assignee:
NEC MICROSYSTEMS LTD
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L21/82; G06F17/50; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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