PURPOSE: To increase the speed of the address function by including plural address cycles in one fundamental cycle.

CONSTITUTION: Address lines YAm and Yan are made negative to discharge corresponding coupling cells C2 and C3, and pixel cells P1 to P4 in cell groups 202 and 204 are turned on. Next, an erase pulse is applied to address lines XA and YAm to discharge an address A of the cell group 204. By this discharge, plasma is diffused to vertical coupling cells C1 and C4 to form wall electric charge. A pair of holding voltages are supplied to erase the cent P1. Next, holding lines XSa and YSa are kept high-voltage and a holding line YSb is kept constant-voltage to discharge the cell C1 of the cell group 204. The cell P2 is not erased until it is reset by a load holding half cycle. Next, the erase pulse is applied to lines XA and YAn to discharge the address A of the cell group 202, and charged electric charge is generated in cells C1 and C4 to erase the cell P1, P3 or P4.