Title:
METHOD AND DEVICE FOR FAULT-RESISTANT EXPONENTIATION IN CRYPTOGRAPHIC SYSTEMS
Document Type and Number:
Japanese Patent JP2014174556
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method of performing fault-resistant exponentiation using an input x and a secret exponent d.SOLUTION: An a priori selected integer r and a chosen random element a of {0, ..., r-1} are used to form an extended base ^x≡x (mod N), ^x≡1+a*r (mod r). In a generalization, for an a priori selected integer t=br(where b is an integer) coprime to a modulus N, a processor has a modular inverse i=Nmod t. The processor generates S2 the extended base by computing ^x=x+N*[i(1+ar-x) mod t], then computes S3 an extended modulus ^N=Nt, computes S4 S=^xmod ^N, verifies S5 if S≡1+dar (mod r) is satisfied, and if and only if it is satisfied, returns S6 the result S=Smod N via an interface.
Inventors:
JOYE MARC
Application Number:
JP2014046353A
Publication Date:
September 22, 2014
Filing Date:
March 10, 2014
Export Citation:
Assignee:
THOMSON LICENSING
International Classes:
G09C1/00
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki