Title:
METHOD AND DIGITAL FILTER ARCHITECTURE FOR FILTERING DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JPH06350399
Kind Code:
A
Abstract:
PURPOSE: To enable the high resolution processing of a digital sampling signal by sampling an input signal based on different filtering mode or operation and adding a digital output from each filtering operation so as to reconstitute an output signal. CONSTITUTION: A 7-bit input signal S1 is impressed to the input terminal of a filter 2, which outputs a 16-bit signal S2 of address-designating the input side of a switch 3. The signal S2 directly fetched from the filter 2 alternately expresses conversion executed by the filtering section of the different transmitting function of the filter 2. The switch 3 is assigned with a task address- designating the signal S3 to an adder circuit 5 and a delay circuit 4. The circuit 4 introduces a delay time equal to a time required for the filter 2 to process a signal. Consequently, the circuit 5 adds the output of the two filtering section of the filter 2 to reconstitute a final signal.
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Inventors:
GOLLA CARLA (IT)
CREMONESI ALESSANDRO (IT)
CREMONESI ALESSANDRO (IT)
Application Number:
JP865394A
Publication Date:
December 22, 1994
Filing Date:
January 28, 1994
Export Citation:
Assignee:
ST MICROELECTRONICS SRL (IT)
International Classes:
H03H21/00; G06F17/10; H03H17/00; H03H17/02; H03H17/06; H04B3/04; (IPC1-7): H03H17/02; G06F15/31; H03H17/06; H03H21/00
Attorney, Agent or Firm:
Soga Doteru (6 people outside)
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