METHOD AND EQUIPMENT FOR OPTIMIZING ADDRESS MAP IN MULTISCALAR EXPANSION - 株式会社ソニー・コンピュータエンタテインメント

Title:

METHOD AND EQUIPMENT FOR OPTIMIZING ADDRESS MAP IN MULTISCALAR EXPANSION

Document Type and Number:

Japanese Patent JP3813624

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a system and a method, for optimizing an address map in multithread processing environment such as multiscalar expansion of a processor supporting a SIMD process.
SOLUTION: A disclosed shared memory 120 is used for multithread-processing a single instruction multidata thread (SIMD) and a multiscalar thread without conflict of an internal thread memory area, and to enable transition to a multiscalar mode from a SIMD mode. A memory area of the shared memory 120 is address-mapped such that the memory area is zigzag-arranged.

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Inventors:

Tsuyoshi Yamazaki

Application Number:

JP2005125341A

Publication Date:

August 23, 2006

Filing Date:

April 22, 2005

Export Citation:

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Assignee:

株式会社ソニー・コンピュータエンタテインメント

International Classes:

G06F9/38; G06F9/34; G06F12/06; G06F15/00; G06F15/80; (IPC1-7): G06F9/38; G06F12/06; G06F15/80

Domestic Patent References:

JP2002222117A
JP11175339A
JP2002366534A
JP2005527036A

Attorney, Agent or Firm:

Masatake Suzuki
Yoshito Muramatsu
Ryota Sano

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