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Title:
METHOD FOR MANUFACTURING FLASH MEMORY ELEMENT
Document Type and Number:
Japanese Patent JP2005311278
Kind Code:
A
Abstract:

To provide a method for forming a dielectric film between gates of a flash memory element capable of preventing a change in thickness of the dielectric film by suppressing a reaction between a floating gate and an oxide film.

The method for forming the dielectric film comprises the steps of forming a silicon film pattern making a floating gate, forming a silicon-fluorine coupling layer on the surface of the silicon film pattern in a fluorine-supplying atmosphere, forming a silicon-nitride coupling layer on the surface of the silicon film pattern by heat treating in a nitride atmosphere, forming a dielectric film including at least one-layer oxide film on the silicon film pattern having a silicon-nitride coupling layer, and forming a condutive film for forming a control gate on the dielectric film.


Inventors:
PARK SOUKU
Application Number:
JP2004189526A
Publication Date:
November 04, 2005
Filing Date:
June 28, 2004
Export Citation:
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Assignee:
HYNIX SEMICONDUCTOR INC
International Classes:
H01L21/318; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; H01L29/94; (IPC1-7): H01L21/8247; H01L21/318; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
JP2005235987A2005-09-02
JPH08116059A1996-05-07
JP2001223282A2001-08-17
JP2004095918A2004-03-25
JP2001217218A2001-08-10
JP2000012806A2000-01-14
Attorney, Agent or Firm:
Shukichi Nakagawa
Hiroyuki Nakagawa