Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
METHOD OF MANUFACTURING INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE
Document Type and Number:
Japanese Patent JP2011101007
Kind Code:
A
Abstract:

To provide an improved method of manufacturing an integrated circuit with both a GaN element and a CMOS element.

An integrated semiconductor substrate structure 100 includes a substrate 11, a GaN heterostructure 20, and a semiconductor substrate layer 30. The GaN heterostructure 20 is present in a first element area, and it is covered at least partially with a protection layer 8. The semiconductor substrate layer 30 is present in a second element area for definition of a CMOS element. At least one of the GaN heterostructure 20 and the semiconductor substrate layer 30 is epitaxially grown and formed in at least one trench of the substrate 11. The GaN heterostructure 20 and the semiconductor substrate layer 30 are laterally juxtaposed.


Inventors:
CHEN KAI
DEGROOTE STEFAN
Application Number:
JP2010243860A
Publication Date:
May 19, 2011
Filing Date:
October 29, 2010
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
IMEC
International Classes:
H01L27/095; H01L21/338; H01L21/8234; H01L27/088; H01L29/778; H01L29/812
Domestic Patent References:
JP2007184549A2007-07-19
JP2008305977A2008-12-18
JP2004281454A2004-10-07
JP2005057284A2005-03-03
JP2008078684A2008-04-03
JP2011035064A2011-02-17
JP2007184549A2007-07-19
JP2008305977A2008-12-18
JPH0334347A1991-02-14
Foreign References:
US20040012037A12004-01-22
US20040012037A12004-01-22
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Mikio Takeuchi



 
Previous Patent: VIDEO SENSOR, AND METHOD OF MANUFACTURING THE SAME

Next Patent: ENERGY HARVESTING DEVICE