METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY

Japanese Patent JP3921363

B2

PROBLEM TO BE SOLVED: To prevent a heat history of the manufacture process of a memory circuit from affecting a well region of a logic circuit, and to prevent introduction of contaminants to a substrate at the time of ion implantation for well region formation in a semiconductor device for which the memory circuit and the logic circuit are consolidated.
SOLUTION: A protective insulating film 13 is formed on a semiconductor substrate 11 and a first resist pattern 51 opening the memory circuit 1A of the semiconductor substrate 11 is formed on the formed protective insulating film 13. Thereafter, with the first resist pattern 51 as a mask, by implanting boron ions through the protective insulating film 13 to the semiconductor substrate 11, a first P well 14 is formed. Then, after removing the protective insulating film 13, a first insulating film 15, a first conductor film 16 composed of polysilicon, and a lower capacity insulating film 17 which is an ONO film, are successively deposited on the semiconductor substrate 11.

Hiroyuki Doi

JP2001248719A

May 30, 2007

August 20, 2001

Click for automatic bibliography generation  

Matsushita Electric Industrial Co., Ltd

H01L21/8247; H01L27/10; H01L27/105; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792

JP2000260966A
JP6163926A
JP11261021A
JP10313106A

Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita

Previous Patent: TEMPERATURE COMPENSATION CRYSTAL OSCILLATOR

Next Patent: MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE