Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2013016557
Kind Code:
A
Abstract:
To reduce TAT and manufacturing costs.
A method of manufacturing a semiconductor device according to an embodiment comprises the steps of: forming a pillar on a foundation layer; forming an insulating layer on the foundation layer using GCIB processing such that the insulating layer covers the pillar and a lowest part of an upper surface of the insulating layer which is lower than an upper surface of the pillar; and polishing the insulating layer and the pillar using a CMP process to the extent of the lowest part of the upper surface of the insulating layer.
Inventors:
SONODA YASUYUKI
SUGURO KYOICHI
YOSHIKAWA MASAHISA
YAMAKAWA KOJI
NATORI KATSUAKI
IKENO DAISUKE
SUGURO KYOICHI
YOSHIKAWA MASAHISA
YAMAKAWA KOJI
NATORI KATSUAKI
IKENO DAISUKE
Application Number:
JP2011146577A
Publication Date:
January 24, 2013
Filing Date:
June 30, 2011
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/768; H01L21/304; H01L21/318; H01L21/3205; H01L21/8246; H01L23/522; H01L27/105; H01L29/82; H01L43/08; H01L43/12; H01L45/00; H01L49/00
Attorney, Agent or Firm:
Kurata Masatoshi
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori