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Title:
METHOD OF MANUFACTURING SILICON WAFER INCLUDING Ar/NH3 RAPID THERMAL ANNEALING PROCESS, SILICON WAFER MANUFACTURED THEREBY, CZOCHRALSKI PULLER FOR MANUFACTURING MONOCRYSTALLINE SILICON INGOT
Document Type and Number:
Japanese Patent JP2003051504
Kind Code:
A
Abstract:

To provide a silicon wafer having controlled defect distribution.

DZs having a sufficient depth inward from the surface of a wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates which act as the intrinsic gettering sites have vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes a first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, DZs between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks which corresponds to a bulk region of the wafer. For such as oxygen precipitate concentration profile, the wafer is exposed to rapid heat annealing in a gas mixture atmosphere comprising NH3 and Ar at about 1200°C or below.


Inventors:
PARK JAE-GUN
Application Number:
JP2002136234A
Publication Date:
February 21, 2003
Filing Date:
May 10, 2002
Export Citation:
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Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
C30B15/20; C30B15/00; C30B15/14; C30B29/06; C30B33/00; H01L21/20; H01L21/26; H01L21/322; H01L21/324; (IPC1-7): H01L21/322; C30B15/00; C30B29/06; H01L21/26
Domestic Patent References:
JP2002543608A2002-12-17
JPH01242500A1989-09-27
JP2003031582A2003-01-31
JP2002110685A2002-04-12
JPH1192283A1999-04-06
Foreign References:
WO2000067299A22000-11-09
Attorney, Agent or Firm:
Masatake Shiga (1 person outside)