Title:
METHOD OF MANUFACTURING WIRING BOARD WITH SOLDER BUMP
Document Type and Number:
Japanese Patent JP2004119895
Kind Code:
A
Abstract:
To provide a method of manufacturing a wiring board having solder bumps in which voids are hardly formed and through which the electrodes of an electronic component can be joined firmly to the soldering pads.
On the surface of an insulating substrate 1, a plurality of soldering pads 3 and solder-resistant resin layers 4 having openings 4a through which the central parts of the pads 3 are exposed are formed. Then the soldering pads 3 are coated with solder layers 21 by dipping the substrate 1 in molten solder, and solder paste 22 is applied to the solder layers 21 by printing. Thereafter, the solder bumps 5 are formed by melting the solder in the solder layers 21 and solder paste 22.
Inventors:
ISHIBASHI HIROBUMI
Application Number:
JP2002284425A
Publication Date:
April 15, 2004
Filing Date:
September 27, 2002
Export Citation:
Assignee:
KYOCERA CORP
International Classes:
H05K3/28; H01L21/60; H01L23/12; H05K3/24; H05K3/34; (IPC1-7): H01L23/12; H01L21/60; H05K3/24; H05K3/28; H05K3/34