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Title:
METHOD FOR PROCESSING WAFER
Document Type and Number:
Japanese Patent JP2009021462
Kind Code:
A
Abstract:

To secure the rigidity of a thin wafer before it is divided into pieces of devices in the device manufacturing process of semiconductor chip and the like having a re-wiring layer on a backside, and preferably form the re-wiring layer on the backside of the chip on a stage of the wafer.

Only a region corresponding to a device formation region 4 where the semiconductor chip 3 is formed on the backside of the wafer 1 is thinned by polishing and etching to form a recess 11 on the backside. An annular salient 12 around the recess 11 allows the rigidity of the wafer 1 to be secured and handling of the wafer to be safely and easily performed at a time when the wafer is transferred to a process where a backside re-wiring layer 40 is formed.


Inventors:
KAJIYAMA KEIICHI
ARAI KAZUNAO
Application Number:
JP2007183935A
Publication Date:
January 29, 2009
Filing Date:
July 13, 2007
Export Citation:
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Assignee:
DISCO ABRASIVE SYSTEMS LTD
International Classes:
H01L21/3205; B24B1/00; H01L21/304; H01L23/12; H01L23/52
Domestic Patent References:
JP2006269968A2006-10-05
JP2002299196A2002-10-11
JP2004281551A2004-10-07
JP2001053218A2001-02-23
JP2003197855A2003-07-11
JP2004221350A2004-08-05
Attorney, Agent or Firm:
Suenari Mikio