Title:
METHOD FOR REDUCING ISO-EFFICIENCY CRITICAL DIMENSION FOR MASK BY POLYMER DEPOSITION AND ETCHING IN THE SAME POSITION
Document Type and Number:
Japanese Patent JP3485501
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To effectively reduce the critical dimension of a semiconductor element by stepwise coating a polymer layer with openings and wires, increasing the ratio of height and width on one wire and one opening with the polymer layer and reducing the critical dimension of photoresist.
SOLUTION: A polymer layer 26 is formed on photoresist 21 by a plasma reactor. The material of the polymer layer 26 is selected by carbon fluoride, hydrocarbon fluoride and carbide. A deposition process and an etching process are simultaneously advanced in the same environment in the plasma reactor. The polymer layer 26 is filled in one structure 25 with stepwise coating ability and it does not coat the base part of one structure 25. Thus, the ratio of height to width in one structure 25 can reduce the critical dimension of photoresist 21 from W6 to W7 by the polymer layer 26 coating photoresist 21 by the increase of the polymer layer 26.
Inventors:
Cai Ming
Jian Lun Yang
Jian Lun Yang
Application Number:
JP22521599A
Publication Date:
January 13, 2004
Filing Date:
August 09, 1999
Export Citation:
Assignee:
Unihua Electronics Co., Ltd.
International Classes:
H01L21/302; C23C16/50; H01L21/027; H01L21/3065; H01L21/31; H01L21/311; (IPC1-7): H01L21/30
Domestic Patent References:
| JP8236506A | ||||
| JP1064886A |
Other References:
【文献】特許2917993(JP,B2)
Attorney, Agent or Firm:
Matsumoto Takemoto (5 outside)