PURPOSE: To realize the high speed working of a microprocessor and to cope with various languages including the high level ones by separating a microprocessor into a main processor and a front end processor, performing the transfer of data via a cache consisting of a FIFO memory, and at the same time translating the instructions via the front end processor.

CONSTITUTION: A main processor 1 is prepared together with a front end processor 2 containing an input/output control means which performs the transfer of data between a memory 3 and a peripheral element 4. The processor 2 outputs the address signal of an address bus 5 and a memory read signal 8 to read an instruction out of a memory 3 to translate it into a combination of instructions of the processor 1. While the processor 1 receives a ready signal 12 from the processor 2 and outputs an instruction cache read signal 13 to read an instruction out of the processor 2 via a local data bus 7. Then the processor 1 carries out the instruction. Thus it is possible to attain the high speed working of a microprocessor and to cope with various languages including the high level ones.