PURPOSE: To constitute a system without increasing its memory capacity unnecessarily by providing a bus cycle switching part among an address output part as an output part for an instruction execution part and a system bus, a data input/output part, and a bus control part, and inputting a data width selecting signal or data width select instruction thereto and varying the bit width of a data bus.

CONSTITUTION: For example, when 8-bit data width is selected, a memory access indication A is converted by a cycle control circuit 11 into a memory access indication B which is outputted twice at timing T1 and timing T2. The memory access indication A is inputted to a high-order/low-order selecting circuit 12 as well and the movement of data is controlled with its output. Namely, a low-order selecting circuit 14 operates at the 1st timing T1 and a switching circuit 15 becomes a low-order side, so the low-order half part of data A is outputted as data B to the low priority side of the data bus, but a high-order selecting circuit 13 operates at the next timing T2 and the switching circuit is coupled with the high-priority side, so the high-order half part of the data A is also outputted as the data B to the low-priority side of the data bus as well.