Title:
MICROWAVE FREQUENCY MULTIPLIER
Document Type and Number:
Japanese Patent JP3833570
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a microwave frequency multiplier that prevents spurious oscillation from being caused due to parasitic inductance of a ground connection conductor to which a control input terminal of a transistor is connected.
SOLUTION: A damping resistor 20 is connected between a drain D of a FET 10 and one terminal T3 of an external output transmission line 13, and a damping resistor 21 is connected between a drain D of a FET 11 and the one terminal T3 of the external output transmission line 13. A source of the FET 10 and a gate of the FET 11 are respectively connected to a ground plate at a rear side of a board via a via-hole. When a multiplied frequency exceeds 20 GHz, the via-hole has parasitic inductances 23, 24.
More Like This:
Inventors:
Tsuneo Tokuman
Application Number:
JP2002150156A
Publication Date:
October 11, 2006
Filing Date:
February 29, 2000
Export Citation:
Assignee:
Udina Device Co., Ltd.
International Classes:
H03B19/14; (IPC1-7): H03B19/14
Domestic Patent References:
| JP3158008A | ||||
| JP7263997A | ||||
| JP10341115A | ||||
| JP7312508A | ||||
| JP4189002A | ||||
| JP11298202A | ||||
| JP358608A |
Attorney, Agent or Firm:
Shinkichi Matsumoto
Previous Patent: WEB OPERATING DEVICE AND IMAGE FORMING DEVICE
Next Patent: DATA DECODER AND DATA DECODING METHOD
Next Patent: DATA DECODER AND DATA DECODING METHOD