To provide an analog/digital mixedly mounted semiconductor device capable of suppressing a circuit current at the time of stopping a clock to low.
The device is provided with an analog circuit 2, a digital circuit 1, a clock stop detecting circuit 14 and a control signal selecting circuit 15. The digital circuit 1 operates in accordance with a clock CK, and outputs an analog circuit control signal S1 for controlling the operation of the analog circuit 2. The circuit 14 detects the stoppage of the clock CK and outputs an analog circuit control signal S2 for stopping the analog circuit 2. Using the signals S1, S2, the circuit 15 selects the signal S1 and provides the selected signal to the analog circuit 2 as an analog circuit control signal S3 when the signal S2 is not ouputted, and preferentially selects the signal S2 and provides the selected signal to the analog circuit 2 as an analog circuit control signal S3 when the signal S2 is outputted.
KOBAYASHI HITOSHI
YOKOYAMA AKIO
Makoto Ito
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