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Patent Searching and Data


Title:
MOS INTEGRATED CIRCUIT DEVICE AND PREPARATION THEREOF
Document Type and Number:
Japanese Patent JPS5656666
Kind Code:
A
Abstract:

PURPOSE: To reduce a leak current throughout the device by a method wherein the threshold voltage of MOSFETs is leveled approximately and thereby the tailing properties which the FET with a large gate width usually has are made excellent in the MOSIC wherein the FETs having large or small gate width respectively are mixed.

CONSTITUTION: A source region 1 having source electrodes 4 on both sides of a gate region 3 provided with a gate electrode 6 and a drain region 2 having a drain electrode 5 are arranged to compose an FET. Next, two FETs are formed on the same semiconductor substrate to compose an MOSIC. On the occasion, when there is any difference in the gate width W of the FETs, the tailing phenomenon wherein the drain current changes logarithmically in relation to the gate voltage at the threshold voltage or below is caused in the FET which has a large width. In order to eliminate this phenomenon, an ion is injected into the FET having a large W/L ratio, where L is the length of the gate and W is the width of the gate, so as to raise the threshold voltage. Thus, the threshold voltage of two FET is leveled approximately, whereby the increase in the leak current is prevented.


Inventors:
MORIMOTO KIYOSHI
Application Number:
JP13389979A
Publication Date:
May 18, 1981
Filing Date:
October 13, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/78; H01L21/8234; H01L27/06; H01L27/08; (IPC1-7): H01L21/265; H01L29/78