MOUNTING STRUCTURE OF SEMICONDUCTOR CHIP

Title:

MOUNTING STRUCTURE OF SEMICONDUCTOR CHIP

Document Type and Number:

Japanese Patent JP2004095879

Kind Code:

A

Abstract:

To provide a mounting structure of a semiconductor chip for easily controlling the deformation amount of conductive particles and improving the electric connection reliability of the semiconductor chip and a substrate main body.

In the mounting structure of the semiconductor chip, a plurality of bumps 16 formed on the semiconductor chip 14 are electrically connected to lead terminals 13 corresponding to a plurality of the bumps 16 formed on the substrate main body 10 through the conductive particles 18 mixed in adhesive 17. Bank-like spacers 19 regulating height sizes of the conductive particles 18 sandwiched by the bumps 16 and the lead terminals 13 in a pressured state are arranged on the lead terminals 13 in confronted regions of the bumps 16 and the lead terminals 13.

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Inventors:

TANIMOTO HIROSHI

Application Number:

JP2002255380A

Publication Date:

March 25, 2004

Filing Date:

August 30, 2002

Export Citation:

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Assignee:

OPTREX KK

International Classes:

H01L21/60; (IPC1-7): H01L21/60

Attorney, Agent or Firm:

Shunsuke Nakao
Takashi Ito
Naoko Okura
Fumari Tamari
Takeyuki Suzuki

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