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Title:
MULTI-POWER SOURCE SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0786905
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption by providing an input control circuit between a high voltage driving IC and a low voltage driving IC and fixing the logical state of the low voltage driving IC with a power saving signal when the driving power source of a high voltage is cut off.

CONSTITUTION: At the time of the input enable of a high voltage driving IC 1, a power saving signal PWD turns 'L'. When a power saving signal PWD 'L' is received at a gate, a TrTN5 for switch suppresses the power consumption of the high voltage driving IC 1 by disconnecting a power source VDD1 of the high voltage driving IC 1 from a power source EB of 5V. An input control circuit 3 is driven by a low voltage power source VDD2 of 3V. At the time of the power saving signal PWD'L', a TrN11 is opened from a ground line GND, a TrP12 is conducted to the low voltage power source VDD2 and thus, the output logic of the input control circuit 3 is fixed at 'H'. Therefore, at a low voltage driving IC 2, the input logic is fixed at 'H', and useless power consumption based on a floating signal is prevented.


Inventors:
SHIRAI YOSHIYUKI
Application Number:
JP22926493A
Publication Date:
March 31, 1995
Filing Date:
September 14, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/82; H01L27/118; H03K19/003; (IPC1-7): H03K19/003; H01L21/82; H01L27/118
Attorney, Agent or Firm:
Keizo Okamoto



 
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