Title:
MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JP2000067020
Kind Code:
A
Abstract:
To reduce the capacity of an instruction memory, and to flexibly assign a program area whose application is required by constituting an instruction memory as a multi-port memory in the constitution of a multi-processor system in which a processor and an instruction memory are mounted one to one.
An instruction port 12 of a processor 1 and an instruction port 13 of a processor 2 are connected with the two ports of a multi-port memory 3 so that a bus port exclusive for each processor can be obtained. Thus, the instruction memory is constituted as a multi-port memory so that the instruction memories of the two processors can be shared.
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Inventors:
ASHIHARA KOJI
SAITO AKIO
UNO KOSUKE
SAITO AKIO
UNO KOSUKE
Application Number:
JP23410998A
Publication Date:
March 03, 2000
Filing Date:
August 20, 1998
Export Citation:
Assignee:
NEC CORP
NIPPON DENKI TELECOM SYST
NIPPON DENKI TELECOM SYST
International Classes:
G06F15/167; G06F9/46; G06F12/00; (IPC1-7): G06F15/167; G06F9/46; G06F12/00
Attorney, Agent or Firm:
Akira Muneaki