To ensure the total capacitance even when a defect, such as a solder crack, is generated on a certain outer electrode in a state wherein a multilayer ceramic capacitor which has respective internal electrodes connected to only one external electrode although a multi-terminal type is employed so as to prevent a marked decrease in ESR while ESL is decreased is mounted on a wiring substrate.
The multilayer ceramic capacitor includes a first same-polarity-electrode-connecting conductor 16 and a second same-polarity-electrode-connecting conductor 17 that are provided inside a ceramic laminate 3. The first same-polarity-electrode-connecting conductor 16 is electrically connected to all of the first outer electrodes 10, and the second same-polarity-electrode-connecting conductor 17 is electrically connected to all of the second outer electrodes 11. Preferably, a plurality of first same-polarity-electrode-connecting conductors 16 and a plurality of second same-polarity-electrode-connecting conductors 17 are successively disposed in the laminating direction inside the ceramic laminate 3.
KAMIOKA HIROSHI
TAKAGI GIICHI
| JP2004273701A | 2004-09-30 | |||
| JP2004235556A | 2004-08-19 | |||
| JP2006253419A | 2006-09-21 | |||
| JP2007059814A | 2007-03-08 | |||
| JP2007201467A | 2007-08-09 | |||
| JP2006210421A | 2006-08-10 |
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