Title:
MULTILAYER PRINTED BOARD
Document Type and Number:
Japanese Patent JP2018010912
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a multilayer printed board, which can reduce labor in the editing work of a print pattern which forms a DUT area (test area), with a reduced editing error, and can increase flexibility in the formation of the print pattern, so that can contribute to quality improvement and a reduced delivery period.SOLUTION: Except for a land 106 with a pad to arrange a chip component such as a bypass capacitor, which is formed on the rear face of the DUT area, a land 103 on which a chip component is not arranged is removed. At the time of etching, the conduction of a through hole is not damaged, if the land is removed. Therefore, at the generation of a print pattern by CAD, it is only necessary to edit a land on which a chip component is to be arranged, which brings about easy print pattern editing work and a reduced editing error.SELECTED DRAWING: Figure 5
Inventors:
MATSUMOTO KAZUYA
TOZAWA YOSHIHIKO
TOZAWA YOSHIHIKO
Application Number:
JP2016137301A
Publication Date:
January 18, 2018
Filing Date:
July 12, 2016
Export Citation:
Assignee:
NIPPON AVIONICS CO LTD
International Classes:
H05K3/46; H05K1/11; H05K3/28; H05K3/40
Attorney, Agent or Firm:
Shinto International Patent Office