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Title:
MULTILAYER PRINTED WIRING BOARD AND METHOD OF MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2007027476
Kind Code:
A
Abstract:

To provide a method of manufacturing a multilayer printed wiring board having a multilayer wiring layer, by which a residue is not generated on the bottom surface of a via hole, and to provide the multilayer printed wiring board.

An inner layer printed wiring board 10 includes an inner layer insulating resin layer 11, inner layer circuit pattern 13, and an inner via-land 14. The inner via-land 14 has the shape of a pattern for connection different from that of a normal wiring pattern in order to perform inter-layer connection. The inner layer circuit patterns 13 are generated by a generation method and a shape which are the same as those for normal generation. The inner layer via-land 14 has inner windows 15 with an inner layer conductive layer removed therefrom in generating.


Inventors:
UENO YUKIHIRO
Application Number:
JP2005208570A
Publication Date:
February 01, 2007
Filing Date:
July 19, 2005
Export Citation:
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Assignee:
SHARP KK
International Classes:
H05K3/46; B23K26/00; B23K26/382; B23K26/40; H05K3/00; B23K101/42
Domestic Patent References:
JP2001358464A2001-12-26
JPH10322027A1998-12-04
Attorney, Agent or Firm:
Yoshiro Kurauchi