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Patent Searching and Data


Title:
MULTILAYER WIRING BOARD AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2001257476
Kind Code:
A
Abstract:

To provide a multilayer printed board whose 1st layer and 4th layer and n-th layer and (n-3)th layer can be connected with high accuracy and in a small number of steps, and a method thereof.

In a multilayer wiring board 1 having (n) layers of four or more, the 1st layer 3 and the 2nd layer 5, the 1st layer 3 and the 3rd layer 9, the 3rd layer 9 and the 4th layer 13, the 1st layer 3 and the 4th layer 13, the n-th layer 19 and the (n-1)th layer 21, the n-th layer 19 and the (n-2)th layer 25, the (n-2)th layer 25 and the (n-3)th layer 29, and the n-th layer 19 and the (n-3)th layer 29 are connected, respectively. Holes 37 of 30 μm in diameter are made in the insulating materials 35 between the respective layers of; the 1st layer 3 and the 2nd layer 5; the 3rd layer 9 and the 4th layer 13; the n-th layer 19 and the (n-1)th layer 21; and the (n-2)th layer 25 and the (n-3)th layer 29, and are filled with copper plating 39 to connect the 1st layer 3 and the 3rd layer 9, the 3rd layer 9 and the 4th layer 13, the n-th layer 19 and the (n-1)th layer 21, and the (n-2)th layer 25 and the (n-3)th layer 29.


Inventors:
IINAGA YUTAKA
Application Number:
JP2000069637A
Publication Date:
September 21, 2001
Filing Date:
March 14, 2000
Export Citation:
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Assignee:
OKI PRINTED CIRCUIT KK
International Classes:
H05K3/42; B32B3/02; H05K3/46; (IPC1-7): H05K3/46; H05K3/42
Attorney, Agent or Firm:
Kuninori Funabashi